Posts tagged "panel"

September 4, 2011

Speaking once again on Parallelism and Computer Science Education at the Intel Developer Forum

As a hiring manager building teams working on modern computer software; I’ve often been disappointed in the lack of a proper foundation in parallel algorithms and architectures being taught in current Computer Science curricula. To that end, I’ve been working with a group called the Educational Alliance for a Parallel Future that aims to improve Computer Science curricula in this critical area. The EAPF is once again convening a panel of educators and industry representatives to talk about this important issue and once again I am delighted to participate.

The panel is entitled: Parallel Education Status Check – Which Programming Approaches Make the Cut for Parallelism in Undergraduate Education? Unlike previous iterations of this panel where we spoke in generalities, this time we’ll be diving a bit deeper into specific technologies that we think are good starting places for educators to introduce to their students.

Here is an excerpt of the abstract:
The industry and research communities face increasing workforce preparedness challenges in parallel (and distributed) computing, due to today’s ubiquitous multi-/many-core and cloud computing. Underlying the excitement over technical details of the newest platforms is one of the thorniest questions facing educators and practitioners — What languages, libraries, or programming models are best suited to make use of current and future innovations? This panel will confront this conundrum directly through discussions with technical managers and academics from different perspectives. The session is convened by the Educational Alliance for a Parallel Future (EAPF), an organization with wide-ranging industry/academia/research membership, including Intel, ACM, AMD, and other prominent technology corporations.

The panel will be presented on September 15th, 2011 at 10:15am as part of the Intel Developer Forum 2011 at the Moscone Center in San Francisco, California. There are free passes for interested educators. Register now for a free IDF day pass using promo code DCPACN1.

My specific take has always been that I am not as interested in grounding in a specific parallelism library or abstraction. The pace of change in this area has only increased over the last few years with the rise of multi-core, GPGPU, HPC and heterogenous computing. Techniques and libraries have arisen, gained adoption, and fallen out of favor one after another.

A developer who only understands how algorithms can be mapped to OpenMP-style libraries is not as useful once the team moves to Grand Central Dispatch or OpenCL. A grounding in traditional task-level parallelism as well as data-parallelism techniques is a starting point. It is important not only to understand what each of them are but the different types of problems that they are each applicable to.

Higher level abstractions like OpenMP are good for introductory courses. However, it is important to understand fully how high-level abstractions map to lower level implementations and even the hardware itself. Understanding the hardware your software runs on is critical to find the best performance for your code. It is also critical to understanding why one particular higher level library might work better than another for a particular task on specific hardware.

Once you understand things like hyperthreading, pThreads, locking mechanisms, and why OpenCL or CUDA maps really well to specific problems, but not to others, then you can return to using higher level abstractions that let you focus on your algorithm and not the details.

If I was a Dean of Computer Science somewhere, I’d look to creating a curriculum where parallel programming using higher-level abstractions was part of the introductory courses using something like C++11, OpenMP or TBB. Mid-level requirements would include some computer architecture instruction. Specifically, how computer architecture maps to the software that runs on top of it. This may also include some lower level instruction in things like pThreads, Race conditions, lock-free programming or even GPU or heterogenous programming techniques using OpenCL. In later courses focused more on software engineering, specific areas like graphics, or larger projects: I’d encourage the students to use whichever tools they found most appropriate to the tasks at hand. This might even include very high level proprietary abstractions like DirectCompute or C++AMP as long as the students could make the tradeoffs intelligently because of their understanding of the area from previous courses.

Given that the panel consists of representatives from Intel, AMD, Microsoft, Georgia Tech as well as myself, I’m expecting this to be a very spirited conversation. I hope to see you there.

More information:
Paul Steinberg’s blog post about the panel
Ben Gaster’s post 

8:56 AM Permalink
September 28, 2010

Recordings from the Intel Developer Forum

Here is the recording from the panel I was on: Parallelism and Education: Navigating through a Sea of Cores with Dr. Daniel Ernst (University of Winsconsin-Eau Claire), Dr. Ryan Newton (Intel), Dr. Mathew Wold (Intel), Dr. Michael McCool (Intel), and Thomas Murphy (Contra Costa College)
http://intelstudios.edgesuite.net/idf/2010/sf/aep/ACAP001/ACAP001.html

After the Panel session, I was on an episode of Teach Parallel on Intel Software Network TV with Dr. McCool, Professor Murphy and Paul Steinberg.

There were a lot of other good panels on educating developers for the current parallel architectures that are archived on the Intel site.

10:21 PM Permalink
August 31, 2010

Parallelism and Education: Navigating Through a Sea of Cores (IDF Panel 9/13/10)

If you are attending the Intel Developer Forum in September and you are interested in education, I’ll be on the panel. “Parallelism and Education: Navigating Through a Sea of Cores” with a great group of other industry and academic folks. Paul Steinberg from Intel has posted an introductory post on his blog introducing some of the topics that we’ll be covering in the session.

I’ll be one of the ones representing the Industry side of the equation. While there seems to be some general agreement on the panel about some certain ground truths, there has been some very lively discussion on how best to educate current and future computer scientists in the new paradigms of parallel programming. This session could be a humdinger.

My personal position is that all software is parallel now. Nearly every system that software runs on, from the lowest end embedded systems, to huge data centers are sporting multi-core processors. However, multi-core computing isn’t the only environment software developers work today. Specialized processing units, like discrete GPUs and CPU/GPU hybrids are now very common across a large range of hardware. Distributed computing is widely used at the high-end. Even web programming is moving parallel with worker threads in javascript and my own team’s Pixel Bender in Flash.

If academia treats parallel programming and data structures like a specialized field of study, walled off into a couple courses and ignored by the general curricula, it will be doing a disservice to its students. A thorough grounding in parallel algorithms, data structures, computer hardware and theory integrated throughout the computer science curriculum is required.

While parallel programming is now a fact of life for software, hardware architectures and programming models are still evolving. Understanding the parallel programming concepts, algorithms and patterns and how they map to current hardware is far more important than the syntax or usage of any development library. Hardware will continue to evolve and new patterns will emerge. Without the grounding of theory mixed with the understanding of the hardware, tomorrow’s professionals will struggle to adapt. While I advocate the usage of libraries like OpenMP, TBB, Ct and Cilk for introductory classes, at some point, I think students need to be exposed to low-level threading, GPGPU programming (at the OpenCL or CUDA level), and SIMD so that they can understand what those libraries are doing for them and evaluate new libraries as they become available.

With a solid educational background, today’s students will be well equipped for tomorrow’s parallel future.

To find the panel, check the IDF Session Catalog. It is currently planned for Monday 9/13 at 11am (following the keynote).

Free passes are available to educators -Enter the code ACAWEB1 when you register.

See you there!

9:11 PM Permalink
December 18, 2009

recordings from my recent panels

He is the panel on Flash Games from MAX 2009 in Los Angeles:

and here is the panel titled “Preparing the world for ubiquitous Parallelism” at the SC09 conference in Portland
Youtube link

3:10 PM Permalink